Pipelined Analog-to-Digital Converters (ADCs) are widely used in high speed communication systems and other applications. A pipelined ADC converts an analog input signal into a digital output signal by generating bits of the digital output signal in multiple pipelined stages. Each stage in the pipelined ADC performs two functions: (1) producing digital output bits; and (2) computing and amplifying a residue signal to be passed on to the next stage.
In the case of the widely used 1.5 bit/stage pipelined ADC architecture, the computation and amplification of the residue signal, Vres[N+1], output by an Nth stage of the pipelined ADC architecture typically implements the operation described in equation (1):
                                          V            res                    ⁡                      [                          N              +              1                        ]                          =                  2          ·                      (                                                            V                  res                                ⁡                                  [                  N                  ]                                            -                              b                ·                                                      V                    REF                                    2                                                      )                                              (        1        )            where VREF is the reference voltage, and b is the sub-ADC output coded as −1,0, or 1.
Typical mechanisms for an accurate implementation of the 2× gain articulated in equation (1) have not been efficient in terms of power usage.
Accordingly, circuits and methods for implementing a residue amplifier are provided.